1. Technical Field
The present invention relates generally to an improved data processing system and method. More specifically, the present invention provides a system and method for accurately modeling an asynchronous interface using expanded logic elements.
2. Description of Related Art
An asynchronous interface is an interface between two independent synchronous clock domains which must communicate with one another. These clock domains may result from circuit elements being clocked by clocks that run at different clock speeds, clock domains clocked at the same frequency but having different clock sources, a single clock source having a clock distribution whose transmission delays are not guaranteed to be identical, and the like. Examples of asynchronous interfaces include asynchronous memory interfaces, asynchronous bus interfaces, and the like. Asynchronous interfaces are being used more often in today's computing technologies since it is often the case that one component operates at a first clock speed while another component, with which data communication is necessary, operates at a different clock speed.
An example block diagram of an asynchronous interface is shown in FIG. 1. As shown, the asynchronous interface typically includes a source element 110 operating in a first synchronous clock domain clk1 which must communicate with a sink element 130 operating in a second synchronous clock domain clk2. Logic 120 is provided as a means for communicating between the two clock domains clk1 and clk2 and constitutes the asynchronous interface between these two clock domains. The logic 120 may be very complex.
During design of such asynchronous interfaces, it is important to be able to verify the operation of these interfaces. There are five conditions that exist in asynchronous interfaces that make verification difficult. These five conditions include clock skew, combinatorial switching hazards, combinatorial glitch hazards, asynchronous latch updates (sometimes referred to as propagation delay), and meta-stability. Clock skew is the time differential between the latest a rising clock edge can occur and the earliest a rising clock edge can occur during one clock period. Because of the differences in clocks of an asynchronous interface, clock skew of each of these clocks, and a potential differential in propagation delay from source to sink, it is possible for one input signal to arrive sooner or later than another input signal to the logic of the asynchronous interface. This leads to the occurrence of combinatorial glitch and switching hazards. Moreover, combinatorial logic may also be sourced by multiple asynchronous clock domains and each transition could independently cause a switch and glitch hazard.
Combinatorial glitch hazards may be generated when one input to the logic of the asynchronous interface transitions faster or sooner than another input to the logic. Combinational switching hazards may be generated when one input is maintained at its current state while another input transitions to another state. If the other input transitions too slowly, the output of the logic may not be the intended output and thus, a switching hazard occurs. These hazards lead to asynchronous latch updates which cause the wrong output signal from the logic gates to be latched into the sink latches.
The difference in clocks and clock skew also leads to meta-stability problems. A meta-stable state is a state that exists between either valid digital logic state. Thus, there is a time period in which the state of the logic is uncertain. The clock, and data transitions can and will occur at any point in time. The meta-stability window is the period of time the sink latch can ‘bounce’ between logical values.
Historically, verification engineers did not have a method of verifying that the design did not have errors due to these conditions. Some methods attempt to classify asynchronous crossing, i.e. asynchronous interface, designs into a pattern of a known standard design template. However, there are many cases where the designs go outside the traditional templates and allow for protocol violations to occur. When such cases arise, the design may ignore the results of the asynchronous crossings, i.e. the asynchronous interface, at some point later in the design, thereby leading to incorrect results.
Thus, it would be beneficial to have a system and method for modeling asynchronous interfaces accurately such that the problems associated with clock skew, glitch hazards, switching hazards, asynchronous latch updates, and met-stability are accounted for in order to verify an asynchronous interface design.